Short circuit constraint altium ошибка

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Hi,

I’ve made some custom pads to better match a manufacturers recommended land pattern.

Every thing is fine unless the pad has no net,
Altium will then report a short circuit between ‘pad on top layer and region on top layer’. (see attached image).

I’ve followed free_electrons advice here

Invoking «Design -> Netlist -> Update Free Primitives From Component Pads…» works,
the regions are assigned the same net as the pads, «No Net»…..

so the violation is still valid.

I’ve tried allowing short-circuits between ‘No Net’ and ‘No Net’, (see attached image)

I’ve also tried Non-Specific No ERC directives in the schematic, (see attached image)

any ideas on how to get around this without assign names nets to every unused pin?

thanks so much for reading!

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Per your layout screen capture, you still have left over objects  connected to the pads. Delete them and you should be fine.

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I am available for freelance work.

From recollection, ‘No Net’ is not actually a net, so using it as an a argument to the InNet() function doesn’t work.  You need to use «Not InAnyNet» to return objects that are not assigned to a proper net.  That’s why your design rule didn’t work, and may be why Altium throws a design rule violation with the default rules in the first place.

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any ideas on how to get around this without assign names nets to every unused pin?

If you are not philosophically opposed to the nets being named and just don’t want to have to do it yourself, you can select the «Allow Single Pin Nets» project option.  Beyond what the name suggests it will also assign named nets to the unused pins for you.  I would think that would make your problem go away with very little effort on your part.

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all fantastic suggestions, I’ll see how I go tomorrow and report back.

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If you are not philosophically opposed to the nets being named and just don’t want to have to do it yourself, you can select the «Allow Single Pin Nets» project option.  Beyond what the name suggests it will also assign named nets to the unused pins for you.  I would think that would make your problem go away with very little effort on your part.

This solves my problem, but I think I am philosophically opposed to the nets being named, or more so, allowing single pin Nets,
by highlighting all net objects with ‘No Net’ I can quickly find faults in the schematic,
e.g. three components are in series and two of them have ‘No Net’ pins, somethings up!

From recollection, ‘No Net’ is not actually a net, so using it as an a argument to the InNet() function doesn’t work.  You need to use «Not InAnyNet» to return objects that are not assigned to a proper net.  That’s why your design rule didn’t work, and may be why Altium throws a design rule violation with the default rules in the first place.

This works and I like it the most,
I assume because this is a short circuit constraint rule,
it won’t stop clearance constraint rules applying to other non net objects?

I’m pretty sure it won’t, but tell me if I’m wrong!

thanks all

Logged

Invoking «Design -> Netlist -> Update Free Primitives From Component Pads…» works,
the regions are assigned the same net as the pads, «No Net»…..

I had the exact problem and doing as you suggested did solve it for me — the nets were all assigned to a common one (GND) in my case, not «no net».  It is possible that I had already manually assigned the pad in the middle of the copper poly region a net name of GND in past edits, so Altium took that as the new net name for the copper poly primitive.

« Last Edit: September 05, 2016, 06:37:41 am by wireworker »

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Why bother adding regions to unused pads ?

If I am not happy with a supplied footprint I copy it to my custom PCB library and edit to my liking, then link it to the part schematic.

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Facebook-free life and Rigol-free shack.

All Contents

The PCB Rules And Violations panel

Summary

Design Rule Checking (DRC) is a powerful automated feature that checks both the logical and physical integrity of your design. The PCB Rules And Violations panel allows easy browsing of the enabled design rules and violations in the current board layout workspace. The panel provides a central point for browsing and editing rules, instigating design rules checks, and viewing individual violations as graphic overlays in the editor workspace.

Panel Access

• To display the PCB Rules And Violations panel, click the Panels button at the bottom-right of Altium Designer when the PCB Editor is active then select the PCB Rules And Violations entry.
• Alternatively, you can access the panel by clicking View » Panels » PCB Rules And Violations.
• When a DRC batch process completes, the PCB Rules and Violations panel automatically launches.

Highlighting Controls

The controls at the top of the panel allow you to apply highlighting, zoom, etc., to design rules/violations in the design space.

• Apply — click to apply the chosen highlighting options to the selected rule.
• Clear — click to clear the highlighting options from the selected rule.
• Magnify — click to open a pop-up that allows you to control the zooming of highlighted objects. Use the slider bar to configure the zooming level.
• Drop-down — select from the drop-down the desired mask/dim highlighting. Choices are: Normal, Mask, and Dim.
• Select — enable to select the rule
• Zoom — enable to zoom to the violation
• Clear Existing — enable to clear the existing highlighting features of the selected rule.

Selecting Rules and Violations

The body of the PCB Rules And Violations panel has four sections, each offering a finer scope of the design rules and violations:

• Rule Classes — Design rules grouped by classes, such as Clearances and Widths.
• Rules — The individual design rules of the selected class. The specific DRC can be run via the right-click menu.
• Violations — Details of each rule violation reported by activated design rules checks.
• Waived Violations — Details of each waived rule violation reported using the Waive Selected Violations command. This section is visible only after at least one violation has been waived.

Waived violations are displayed on the board in a separate color from other violations. Color settings can be changed in the System Colors region of the View Configuration panel.

Selecting an individual rule violation causes the design workspace to graphically highlight that violation. Enhanced violation graphics are drawn only on the layers on which the offending primitives reside, and that layer (if enabled) will become the active layer in the workspace. When the rule violations details are enabled (see below), the editor’s graphics will display the constraint value defined for the rule and indicate how the offending primitive(s) are either below or above this value.

Violation of a minimum Width rule set to 12mil.

Violation of a Via dimension rule set to minimums of 50mil diameter and 28mil hole size.

Note that if you have the Zoom highlighting method enabled, the workspace will be zoomed-in to fit the browsed violation for a much more precise ‘view’ of the violating area. The level of that zoom can be varied via the panel’s Magnify button.

You can also directly access violations from within the design space. With the cursor over an offending primitive, right-click and select Violations from the context menu, then select the appropriate violation to open the  Violation Details dialog.

Controlling the Display of DRC Violations

The visual display of DRC violations can be configured to maximize clarity and/or suit your own preferences by setting the style, number and color of the graphic markers. Along with the graphic display of violation details, the design primitives can be overlaid with a graphic pattern selected from a number of styles.

Top: Violation details enabled. Middle: Violation error overlay enabled.
Bottom: Both details and error overlay enabled.

Violation Display Preferences

Control over how DRC violations are displayed using the custom violation graphics and/or a defined violation overlay is specified on the PCB Editor – DRC Violations Display page of the Preferences dialog.

Choose how you want DRC violations to be displayed in the workspace — using custom graphics and/or a defined violation overlay.

Specifying the Overlay Style

Use the options in the Violation Overlay Style region of the page to specify the style of violation overlay to use. The table below illustrates example results for a routed track on the Top Layer in violation of a Width rule based on the chosen violation overlay style.

The override color (the color associated with the display of a violation overlay) is that defined for the DRC Error Markers system color in the System Colors region of the Layers and Colors tab of the View Configuration panel.

Specifying Violation Display Style for each Rule Type

The Choose DRC Violations Display Style region of the dialog presents a grid allowing you to choose the display style used on a per-rule basis. Enabling the Violation Details field for a rule type will use the associated custom violation graphics to display the DRC violations of that rule. Enabling the Violation Overlay field will display the violations using the specified overlay style.

Right-click within the grid to access a menu of commands to quickly enable or disable use of a violation display type for all rule types. You can also quickly enable the display of violations – detailed graphics or overlay styles – for only those rules currently being used in the design.

Use the grid and related commands to set up exactly how DRC violations will be displayed in the workspace.

By default, the Violation Details display option is enabled for all rule types and the Violation Overlay display option is enabled only for Clearance, Width and Component Clearance rules.

Using the two display types together can prove useful in terms of providing a ‘coarse’ and ‘fine’ indication of violations.

Right-Click Menus

The entries in each section of the panel offer a range of options via the right-click context menu. Notable right-click options for each section are:

Rule Classes

• Run DRC Rule Class — runs all rules contained in the class. Classes may only contain a single rule (such as Short-Circuit Constraint) or a large number (typically, the Clearance Constraint class).
• Clear Violations For Rule Class — clears the violations (both graphically and listed in the panel) for all rules contained in the class.

Rules

• Run DRC Rule — runs the selected rule.
• Clear Violations — clears the violations reported by the selected rule.
• Properties — opens the Edit PCB Rule dialog that allows the rule configuration to be changed on the fly.

Violations

• Properties — opens the Violation Details dialog, which provides full details of the rule constraint and the current violation.

• Waive Selected Violations — opens the Waived Violation Info dialog in which information can be entered and saved about the violation selected to be waived. After entering the necessary information and clicking OK, the waived violations are displayed under the Waved Violations region.

Notes

• For full access to the PCB Constraint Classes and Rules, open the PCB Rules and Constraints Editor dialog by clicking Design » Rules.
• Online Design Rule Checking can be enabled/disabled in the PCB Editor — General page of the Preferences dialog.
• Design Rules can be individually enabled for Online or Batch checking (or both) in the Design Rule Checker dialog (Tools » Design Rule Check).

• Violated Rule — this area presents the design rule that is being violated, for the violation entry currently selected in the list above. The rule is displayed in terms of its type, violated constraint(s), and scoping.
• Violating Primitives — this area presents the primitives involved in the currently selected violation, in terms of object type, identifier (where applicable), location, and layer upon which they reside.
• Waive this violation — enable this option to waive the violation
  • Created At — lists the date and time the violation was waived.
  • Author — lists the user who waived the violation. This information is auto-filled using your account information and can be edited manually.
  • Reason — manually enter text explaining the reason for waiving the violation.
• Highlight — click this button to have the primitives involved in the currently selected violation momentarily highlighted in the workspace. Highlighting essentially leaves the offending primitives in their normal visibility with all other objects in the workspace becoming temporarily monochromatic.
• Jump — click this button to quickly jump to the offending primitives for the currently selected violation in the workspace. The primitives will effectively be zoomed and centered within the design space.